EPM7064SLC44-10N

44-PLCC, PLD, –2.0V to 7.0V, –25mA to 25 mA, EPM7064SLC44-10N, Altera

Rated 5 Rating 5 | reviews | Write a review

Price:: US $1.00~99.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $1.00~99.00

PartNumber:: EPM7064SLC44-10N

Brand:: Altera Corporation - ALTR | Pack: PLCC | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Mr. David's store

(China (Mainland))

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2012-07-22

From Other Seller

Part Number:EPM7064SLC44-10N
US $1.00 - 99.00
YL-G709

US $65.00 - 68.00 / Piece
(0) Remove
HEF4051BT

US $0.15 - 1.20 / Piece
(0) Remove
Quantity:

piece

Product Summary

The EPM7064SLC44-10N is a high-density, high-performance PLD. It is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7064SLC44-10N provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. The EPM7064SLC44-10N has several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect esources, fast input registers, and a programmable slew rate.

Parametrics

EPM7064SLC44-10N absolute maximum ratings: (1)Supply voltage: –2.0V to 7.0V; (2)DC input voltage:–2.0V to 7.0V; (3)DC output current, per pin: –25mA to 25 mA; (4)Storage temperature:–65℃ to 150℃; (5)Ambient temperature:–65℃ to 135℃; (6)Junction temperature:Ceramic packages, under bias:150℃,PQFP and RQFP packages, under bias:135℃.

Features

EPM7064SLC44-10N features: (1)High-performance, EEPROM-based programmable logic devices(PLDs) based on second-generation MAX architecture; (2)5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices:ISP circuitry compatible with IEEE Std. 1532; (3)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (4)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (5)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates; (6)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (7)PCI-compliant devices available; (8)Open-drain output option in MAX 7000S devices; (9)Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls; (10)Programmable power-saving mode for a reduction of over 50% in each macrocell; (11)Configurable expander product-term distribution, allowing up to 32 product terms per macrocell.